Such voltage reference circuits compensated for non-linearity in temperature characteristic of diode have appeared from time to time but until recently there have been no proposals capable of convincing experts in this field. Now, however, proposals capable of persuading such experts are being made.
A first of such proposals is that by Brokaw, an elder in the field. A second is by the present inventor (Kimura), who holds the largest number of registered patents in the field. The characterizing feature of the first and second proposed circuits is that both utilize a circuit network, which comprises diodes and resistors, as a circuit block that is capable of compensating for the non-linearity in non-linearity in temperature characteristic of diode. A third proposal is a circuit developed by Ker et al. from National Chiao-Tung University in Taiwan.
The Brokaw circuit, which is the first proposed circuit mentioned above, will be described first with reference to FIG. 6. In the specification of Patent Document 1 (US2005/0194957A1), many equations are set forth and temperature characteristics are described. Here we will limit our discussion to what is illustrated in FIG. 6.
In FIG. 6, let the forward voltages of diodes D1 and D2 be represented by VBE1 and VBE2, respectively. An error-voltage amplifying circuit AP1 operates so as to control the gate voltage of p-channel MOS transistors M1 and M2 in such a manner that voltages VA and VB at differential input terminals of the error-voltage amplifying circuit AP1 will be equal.
Accordingly, we have the following:VA=VB=VBE1  (1)
If we assume that V1 is the voltage at a common connection node of resistors R1, R2 and R3, then a current IR1 that flows into resistor R1 is given by Equation (2) below.IR1=(VBE1−V1)/R1=ΔV1/R1  (2)
Further, a current IR2 that flows into resistor R2 is given by Equation (3) below.IR2=(V1−VBE2)/R2=ΔV2/R2  (3)
A current IR3 that flows into resistor R3 is given by Equation (4) below.IR3=V1/R3  (4)
Equation (5) below holds with regard to current.IR1=IR2+IR3  (5)
The relation indicated by Equation (6) below holds in view of Equation (5) and Equations (2) to (4).ΔV1/R1=ΔV2/R2+V1/R3  (6)
If temperature characteristics are taken into consideration, the forward voltage VBE1 of diode D1 will have a negative temperature characteristic (the value of the temperature coefficient is negative), as is well known. Moreover, the lower the temperature, the smaller the slope of this temperature characteristic becomes. This is a cause of problematic non-linearity.
If it is assumed for the sake of simplicity that resistors R1, R2, and R3 (, R4) have no temperature characteristic, then a current I3 supplied from a transistor M3 will be proportional to a current I2 supplied from transistor M2 and is given by the following:I2=IR1(=ΔV1/R1)  (7)
Owing to the fact that VREF (=I3R4) does not possess a temperature characteristic, voltage V1 at the common connection terminal of resistors R1, R2 and R3 becomes a voltage smaller by a constant voltage value than the forward voltage VBE1 of diode D1. If illustrated, the voltage will be a curve obtained by a downward parallel translation of VBE1.
On the other hand, in view of Equation (6), the forward voltage VBE2 of diode D2 comes to possess an even greater negative temperature characteristic so as to cancel out the negative temperature characteristic of V1. That is, it will be understood that the temperature characteristic cannot be cancelled out unless the voltages become voltages having temperature characteristics of the kind shown in FIG. 7.
FIG. 8 illustrates SPICE simulation values (the temperature characteristic of an output voltage Vref) of the circuit (see FIG. 6) according to Brokaw. As depicted in FIG. 8, a temperature deviation of ±0.15% is obtained over a 190° C. temperature range of −55° C. to 135° C.
Next, the circuit according to Kimura (Japanese Patent Application No. 2005-016902 (Japanese Patent Kokai Publication No. JP-P2006-209212A)), will be described. As shown in FIG. 9, the forward voltages of diodes D1 and D2 are represented by VBE1 and VBE2, respectively. An error-voltage amplifying circuit (differential amplifying circuit or operational amplifier) AP1 operates so as to control the gate voltages of transistors M1 and M2 in such a manner that voltages VA and VB at differential input terminals of the error-voltage amplifying circuit AP1 will be equal.
Accordingly, we have the following:VA=VB=V1  (8)
Here, a current IR1 that flows into a resistor R1 and a current IR3 that flows into a resistor R3 are represented by Equations (9) and (10), respectively, below.IR1=(V1−VBE1)/R1=ΔV1/R1  (9)IR3=(V1−VBE2)/R3=ΔV2/R1  (10)
If it is assumed for the sake of simplicity that resistors R1, R2, R3 and R4 (, R5) have no temperature characteristic and that the IR1 and IR3 have no temperature characteristic, then the following will hold in case of IR1=IR3:ΔV1/R1=×V2/R3  (11)
Accordingly, since both sides of Equation (11) possess no temperature characteristic, both VBE1 and VBE2 become voltages smaller by constant voltage values than V1. If illustrated, the voltages will be curves respectively obtained by downward parallel translations of V1.
That it, it will be understood that the temperature characteristic cannot be cancelled out unless the voltages become voltages having temperature characteristics of the kind shown in FIG. 10.
The SPICE simulation values of this circuit are illustrated in FIG. 11. This is for a case where, when the power-supply voltage is 1.2 V, R1=1.2 KΩ, R2=70 KΩ, R3=2.408 KΩ, R4=38 KΩ and R5=20 KΩ hold, two diodes D1 and D2 are connected in parallel (X2) as unit diodes, the transistors M1, M2 and M3 are made equal and the current mirror ratio is made 1:1:1. The voltage obtained will be 542.5 mV at −46° C., 541.2 mV at 27° C. and 542.4 mV at 100° C., and the temperature characteristic is +0.185% over a temperature range of 140° C. The minimum voltage is at ordinary temperature (27° C.) and the voltage rises minutely at low (−46° C.) and high temperatures. Hence the temperature characteristic obtained has a very slight bowl-shaped appearance.
Although an inverted bowl shape was initially obtained in the SPICE simulation, the temperature characteristic could be linearized by changing the value of resistor R3. It so happened that in the case of the values cited above, the curve somewhat exceeded a straight line and the bowl-shaped temperature characteristic resulted.
The circuit according to Ker et al. will be described next. The circuit according to Ker et al. (see FIG. 3 of Non-Patent Document 1) illustrated in FIG. 12 is described as using two Banba circuits, one of p-channel (p-ch) and one of n-channel (n-ch), in which the difference between the output currents of the two circuits is calculated and the temperature characteristic cancelled. FIG. 13 is a diagram useful in describing the mechanism that is at work [see FIG. 2 of Non-Patent Document 1 and FIG. 7, etc., of Patent Document 2 (US2005/0264345 A1)].
As illustrated in (A) of FIG. 13, a Banba circuit, which includes a diode-connected pnp transistor (band gap reference A with pnp BJTs) and a current mirror circuit composed of n-ch transistors M3 and M4, is adopted as a first reference current circuit for output current I1, a Banba circuit, which includes a diode-connected npn transistor (band gap reference B with npn BJTs) and a current mirror circuit composed of p-ch transistors M1 and M2, is adopted as a second reference current circuit for output current I2, and the output current I1 of the first reference current circuit is subtracted from the output current I2 of the second reference current circuit to obtain the following:ΔI(=I2−I1)  (12)
As illustrated at (B) and (D) of FIG. 13, the output currents I1 and I2 of the first and second reference current circuits both exhibit bowl-shaped temperature characteristics. However, with an ordinary circuit of this type such as the Banba circuit (Patent Document 3), it is reported that the temperature characteristic becomes a bowl of inverted shape.
In order for the following to hold:I1<<I2  (13)with regard to the output currents I1 and I2 of the first and second reference current circuits, it goes without saying that it is necessary to make the number of diodes connected in parallel and resistance values in the first reference current circuit very different from those in the second reference current circuit. However, this does not mean that the characteristics of the pnp transistor and p-ch transistor will coincide with the characteristics of the npn transistor and n-ch transistor, and to what extent cancellation can be achieved is in doubt.
The Banba circuit is illustrated in Patent Document 3 (Japanese Patent Kokai Publication No. JP-A-11-45125) or Patent Document 4 (U.S. Pat. No. 6,160,391).
Reference is usually had to the Banba et al. paper (“A CMOS Band-Gap Reference Circuit with Sub IV Operation,” 1998 IEEE Symposium on VLSI Circuits, Digest of Technical Papers 19.3, pp. 228-229, or the full paper in IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 670-674, May 1999). However, although the way in which input voltages to the error-voltage amplifying circuit are divided respectively by associated resistors R1a, R1b, R2a and R2b shown in FIG. 12 (where R1b-NPN and R2b_NPN have been interchanged) and set to voltage values obtained by the division of diode voltages, is exactly same as that shown in FIG. 6 of the Banba patent specification (FIG. 8 of the U.S. patent), it is not described in the Banba et al. paper mentioned above. For this reason it is often referred to as the work of other publishers of papers from Japanese Patent Kokai Publication No. JP-A-11-45125 onward and, moreover, from publication of the Banba et al. paper onward. This circuit is old and is an application filed on Jul. 29, 1997. The invention precedes that date.
The circuit shown in FIG. 12 (FIG. 3 in Non-Patent Document 1) is an arrangement in which two Banba circuits of different polarities are combined. In the first reference current circuit, if nPNP is assumed to be the area ratio of the two diode-connected pnp transistors (Q1_PNP, Q2_PNP), the current I1 will be represented by Equation (14) below.I1=[VBE2—PNP+(R2—PNP/R3—PNP)VT ln(nPNP)]/R2—PNP  (14)
In Equation (14), we have the following:R1—PNP=R1a—PNP+R1b—PNP=R2—PNP=R2a—PNP+R2b—PNP  (14.1)
Further, in Equation (14), VBE2_PNP is a base-emitter voltage of Q2_PNP, and VT is a thermal voltage.
Similarly, in the second reference current circuit, if nNPN is assumed to be the area ratio of the two diode-connected npn transistors (Q1_NPN, Q2_NPN), the current I2 will be represented by Equation (15) below.I2=[VBE2—NPN+(R2—NPN/R3—NPN)VT ln(nNPN)]/R2—NPN  (15)
In Equation (15), we have the following:R1—NPN=R1a—NPN+R2b—NPN=R2—NPN=R2a—NPN+R1b—NPN  (15.1)
Further, in Equation (15), VBE2_NPN is a base-emitter voltage of Q2_NPN, and VT is a thermal voltage.
It should be noted that what is correct in Equation (15.1) is R1_NPN=R1a_NPN+R1b_NPN=R2_NPN=R2a_NPN+R2b_PNP.
If the error in writing is corrected, Equations (14) and (15) will be the same and the PNP side and NPN side will be the same.
The expression in the bracket in Equation (14) or (15), namely [VBE2_PNP+(R2_PNP/R3_PNP)VT ln(nPNP)], or [VBE2_NPN+(R2_NPN/R3_NPN)VT ln (nNPN)] is an expression illustrated in a circuit analysis formula of a reference voltage generating circuit of this kind, namely a reference voltage generating circuit that is known as the invention of Dobkin et al. (U.S. Pat. No. 3,617,859), the so-called “Widlar bandgap voltage reference” named after one of the co-patentees.
That this reference voltage generating circuit is named not after the head (first) inventor but after the co-inventor (second inventor) also is odd. The reason is a paper authored solely by the co-inventor (second inventor) (R. J. Widlar, “New Developments in IC Voltage Regulators,” IEEE Journal of Solid-State Circuits, Vol. SC-6, No. 1, pp. 2-6, February 1971). In actuality, however, the circuit analysis formula of the U.S. Patent and technical paper is not a relational expression between Q1(VBE1) and Q2 (VBE2) directly related to a reference voltage generating voltage, but is a relational expression between Q3(VBE3) that controls Q1 and Q2 and Q2 (VBE2) directly related to a reference voltage generating voltage, wherein the expression is written using VBE1 instead of VBE3. Specialists in this field find this difficult to understand.
A self-bias method was subsequently used in reference voltage generating circuits of this kind and the fact that equal currents are passed through the transistors Q1 and Q2 became readily understandable in terms of circuit operation.
In a reference voltage generating circuit of this kind, the reference voltage that is output is indicated by an equation in which either of the VBE voltages and the difference voltage (ΔVBE) between the two VBE voltages are weighted and added. That is, the expressions within the brackets of Equations (14) and (15) correspond to this equation.
In Equation (14), we have the following:ΔVBE=VT ln(nPNP)  (16)
In Equation (15), we have the following:ΔVBE=VT ln(nNPN)  (17)
As is well known, ΔVBE has a positive temperature characteristic, and VBE has a negative temperature characteristic (temperature coefficient) of about −1.9 mV/° C. Accordingly, the temperature characteristic can be cancelled out by weighting and adding ΔVBE and VBE. VT is 26 mV at ambient temperature (i.e., at about 300 K (absolute temperature)), while VBE is assumed to be 600 mV at ambient temperature. More specifically, the temperature characteristic of the expression: ΔVBE+(R2/R3)VT ln(n), which corresponds to the one within the brackets of Equations (14) and (15), is able to be compensated, when the value of the weighted sum of −1.9 mV and (26 mV/300) become zero. The weighting therefore is set to:21.9[=1.9 mV/(26 mV/300)]  (18)
Since the weighting corresponds to (R2/R3)ln(n), we have the following:(R2/R3)ln(n)=21.9  (19)
This 21.9 is distributed to the resistor ratio (R2/R3) and to the logarithmic value ln(n) of the emitter area ratio n.
This is correct as a primary approximation. However, when the secondary effects of the negative temperature characteristic of VBE are considered, the output voltage of the reference voltage generating circuit generally becomes an inverted bowl-shaped characteristic in which voltage is not cancelled out completely but declines regardless of whether temperature rises or falls from ordinary temperature.
In the circuit according to Ker et al., I1 [Equation (14)] is subtracted from I2 [Equation (15)]. However, since a difference appears, naturally it is necessary to set I1 and I2 so that I2>I1 will hold.
In Equations (14) and (15), however, R2 is a resistor that converts the reference voltage to a current, although originally this is a resistor for weighted addition for the purpose of compensating for the temperature characteristic of the reference voltage. Accordingly, in order to set the output currents to I2>I1, naturally it is necessary to make the emitter area ratio n very different between the NPN and PNP sides.
More specifically, the following holds:R2—NPN<R2—PNP  (20)Therefore, if we assume the following for the sake of simplicity:R3—NPN=R3—PNP  (21)then it is necessary to set nNPN and n-PNP as follows:nNPN>>nPNP  (22)
Further, that NPN and PNP, which are of different polarities, will have characteristics that coincide is inconceivable.
It should be noted that although a reference current circuit so adapted as to not possess a temperature characteristic by combining a PTAT (proportional to absolute temperature) and an inverse PTAT circuit is disclosed in FIG. 4 of Patent Document 5 by the present inventor, it should be added that compensation for non-linearity (non-linearity in the temperature characteristic) of a diode is not carried out.
[Patent Document 1] US Patent Specification US 2005/0194957 A1
[Patent Document 2] US Patent Specification US 2005/0264345 A1
[Patent Document 3] Japanese Patent Kokai Publication No. JP-A-11-45125
[Patent Document 4] US Patent Specification U.S. Pat. No. 6,160,391
[Patent Document 5] Japanese Patent Kokai Publication No. JP-A-8-123568
[Non-Patent Document 1] M.-D. Ker et al., “New Curvature-Compensation Technique for CMOS Bandgap Reference with Sub-1-V Operation,” (IEEE ISCAS' 05), Publication Date 23-26, May 2005 FIG. 3
The voltage reference circuits described above with reference to FIGS. 6, 12 and 13 have the problems set forth below.
The first problem is a large variation. The reason for this is characteristics do not coincide because use is made of diode-connected NPN and PNP transistors the polarities of which differ.
The second problem is that it is difficult to achieve a high precision. The reason for this is that it is attempted to perform cancellation by reference current circuits having temperature characteristics of small non-linearity. This makes it difficult to obtain a high precision.